At Oriole Networks, we are developing disruptive technologies for AI/ML and HPC networking that will revolutionise Data Centers. These technologies will speed up training and inference while dramatically reducing energy consumption for a sustainable future. 

• Microarchitecture definition in collaboration with the broader team. 

• Preparing detailed technical documentation and presentations to stakeholders. 

• RTL Implementation, synthesis, timing closure.

• Unit verification planning and simulation testing using SystemVerilog.

• Delivering and validating FPGA-based lab setups for customer trials.
  
  

• Extensive hands-on industrial experience of FPGA design for network applications at 100Gbps and above. 

• Experience with high-performance FPGA devices:  Xilinx Versal Premium.

• Bare metal use of high-speed transceivers  such as GTM/GTY.

• Experience and good understanding of  packet processing and MAC protocol, PTP etc. Experience using PCIe (at least 4th gen) though it is optional. 

• Strong knowledge of FPGA tool flows (synthesis, partitioning, place&route, timing analysis). 

• Comprehensive understanding of clock domain crossing techniques. 

• Strong knowledge of FPGA debug tools such as JTAG/ILA. 

• Excellent skills in SystemVerilog/Verilog/VHDL. 

• Experience using  simulation tools such as Questa, ModelSim, Vivado and Vitis. 

• Scripting and automation, such as TCL and Python. Efficient in C/C++. 

• A humble attitude and good communication skills. 

• Ability to create an understanding of complex ideas, concepts and designs to a variety of audiences from multiple backgrounds. 

• Bachelor or Master degree in electronics engineering, physics, or other relevant fields or experience within the industry.